This invention relates to a processor architecture, and in particular to a processor architecture which is particularly useful in signal processing applications.
Modern high-performance wireless communications systems require digital processors which can provide billions of compute operations per second to achieve acceptable performance, for example to carry out operations such as filtering, equalisation and decoding functions. Increasingly these very high processing demands are satisfied by the use of multiple execution units (such as arithmetic logic units (ALUs), multipliers, address generators etc.) which can operate in parallel within a single processor cycle, and can thus increase the aggregate number of operations which can be completed per cycle.
One architectural approach which has been developed, in order to allow parallel operation of multiple execution units, is the Long Instruction Word (LIW) architecture. In this approach, instructions for each of a number of execution units are concatenated into one “long instruction word” which can be executed in a single processor cycle. Typically, in implementations of this approach, a bit field within the long instruction is reserved for an instruction for each of the execution units, regardless of whether a particular execution unit will be active within any one processor cycle. This has the disadvantageous effect that it creates excessively long instruction words, which can contain a lot of redundant information for execution units that are not active. The end result is a larger and more costly design.